1. Field of the Invention
The present invention relates to a stack pointer control circuit for saving information stored in a predetermined register into a stack memory or returning the information read from the stack memory to the predetermined register.
2. Description of the Prior Art
In a subroutine call instruction or a return instruction for computers, there exists such an operation that saves a value of a program counter into a stack memory or returns the saved value from the stack memory to the program counter or such an instruction that saves a value of a specific register into a stack counter or returns the saved information from the stack counter to the specific register as in a push instruction or pop instruction. Further, a push-all instruction and a pop-all instruction such that values in plural or all registers are saved to the stack memory or returned from the stack memory at the same time are effective instructions when an interrupt processing is effected, for instance.
The stack pointer is a circuit for designating an address of a stack memory to which register information is saved or for designating an address of a stack memory from which the stored information is returned to the register. However, in a stack pointer for push-all instructions or pop-all instructions, plural addresses of the stack memory at which plural register values are to be stored or plural addresses of the stack memory at which plural values to be returned to the plural registers are stored should be determined in sequence.
In the stack memory available for the push-all or pop-all instructions, a memory capacity for storing a plurality of values is necessary to store values of plural registers, and a push-all or a pop-all instruction is enabled within a range of the memory capacity. However, when the push-all instruction is executed in excess of the memory capacity of the stack memory, or particularly when a so-called stack underflow occurs such that the push-all instruction is executed in excess of the memory capacity of the stack memory during the push-all instruction operation and therefore there exist no memory locations to which register values are saved in the stack memory, an interruption occurs for processing this stack underflow. The above problems also arise in the pop-all instruction in the same way as in the stack underflow of the push-all instruction. That is, when a plurality of values are read out of the stack memory in sequence to return the values stored in the stack memory to the register, if so-called stack overflow occurs such that address information is read back in excess of the upper limit of the stack memory, for instance, an interruption occurs for processing this stack overflow. Interruptions which occur during the execution of the push-all instruction or the pop-all instruction are not necessarily limited to the above-mentioned stack overflow or underflow; but, various interruptions due to other reasons often occur. Therefore, the stack control instructions such as the push-all instruction or pop-all instruction are often interrupted during the processing due to the occurence of these interruptions.
As described above, in case an interruption occurs during the execution of a stack control instruction, the CPU enters an interrupt processing routine during the stack control instruction operation to execute an interrupt processing. However, since the stack control instruction has already been executed midway, a stack memory address at the time of this interruption is kept stored in the stack pointer. In more detail, the assumption is made that during the operation of a stack control instruction for saving 10 register values to a stack memory, an interruption occurs and the saving processing to the stack memory is interrupted after 6 register values have been saved to the stack memory, so that the CPU enters an interrupt routine. In this state, the stack pointer is kept designating an address of the stack memory at which the succedding 7th address value is to be saved. Under these conditions, when the interrupt processing has been executed, in usual the CPU is so determined as to execute again the interrupted stack control instruction beginning from the start. However, at this moment, since the stack memory address designated by the stack pointer is that to which the 7th register is to be saved as described above, the stack pointer is not designating the first address corresponding to the time at which the stack control instruction starts. That is, since the stack memory address designated by the stack pointer does not match that obtained at the start of the instruction execution, there exists a problem in that various program errors occur such that a register value is saved to a different stack memory or information is returned from a different stack memory to the register in accordance with the stack control instruction executed again after the interrupt processing has been completed.
In this case, if the cause of interruption is limited to the stack overflow or underflow, there may exist a method of executing the instruction after having previously confirmed whether the stack areas to be pushed or popped are secured or not. However, in this method, there still exists a problem in that it takes time to confirm the stack areas and further it is impossible to completely cope with the interruption when the interruption results from other reasons.